ATE for digital integrated circuits are required to provide digital stimulus to the integrated circuit (IC) and to measure the resultant digital response from the IC. One goal of this testing is to verify that there are no defects present in the IC that could affect its ability to perform its intended function. A second objective of testing is to verify that the IC will operate under its specified timing conditions. That is, verify that an IC not only performs the correct function, but performs it fast enough to meet its specification.
Prior Art FIG. 1 depicts a diagram 100 of a simplified synchronous digital IC. The IC structure comprises a clock input 105, digital input pins 110, internal data storage elements 115 (data registers), combinatorial logic 120(gates, multiplexers, etc.) and digital output pins 125.
Prior Art FIG. 2 shows a diagram 200 of the operation of the data registers 115 of Prior Art FIG. 1. The data input 205 to the data register 210 is captured on the rising edge 215 of each clock cycle of the clock input signal 220 and transferred to the register output 225. Thus, data is shifted from one register to another on each clock event. While the example depicted is rather simple, actual IC designs typically employ several hundred input/output data pins and several thousands of internal registers.
Prior Art FIG. 3 depicts several critical timing parameters that are tested on the typical digital IC. A specification on any IC pin may or may not be different from the other pins.
For the clock input 305, tcycle specifies the minimum period of time in which data can be transferred from one internal register output, through the combinatorial logic circuitry, and into the next internal data register.
For data input signals 310, tsu, is the minimum amount of time that stimulus data must be valid at the input of the IC prior to the clock transition to ensure that the correct data state will be captured. For data input signals 310, tdh is the minimum amount of time that stimulus data must be held valid at the input of the IC after the clock transition to ensure that the correct data state will be captured.
For data input signals 315, tpd is the maximum amount of time (e.g., the maximum propagation delay) that IC output data takes to become valid at the output after the clock transition.
For data output signals 315, tdoh is the minimum amount of time that IC output data will maintain its previous state at the output of the IC after to the clock transition.
The method used to test the IC described above is referred to as functional testing. Functional testing requires that the test system simultaneously provide input data on all of the inputs pins at the specified data rate, and under the specified timing conditions. The tester is also required to compare the data outputs at the specified times against expected data results. Since an IC may have several hundred input/output signals, and potentially require more complex timing than described above, the complexity of test systems used for functional testing can be very high.
Prior Art FIG. 4 depicts a diagram 400 of a conventional test system used to perform functional testing. A common programmable Cycle Generator 405 establishes the test pattern data rate (tcycle) and addresses the test pattern memory 425 through and address pointer 406. Each individual tester pin 410 is implemented with multiple independently programmable timing generators in order to generate the precise timing events required. Each tester pin may typically each have 3-6 timing generators 415. Another capability implemented is the ability to dynamically select different cycle and timing values from one cycle to another from a finite set of values stored in a memory 420 (referred to as Time set memory). The Time set memory location is selected on each data cycle by dedicated bits output by the test pattern memory 425 over a time set memory address bus 430. Depending on the specific implementation, the test pattern memory 425 may provide a unique address for each pin's time set memory, or a common address for all pins.
The most common design for test (DFT) implementation is scan based design. To address the problems of increasing IC complexity and test cost, some IC manufacturers incorporate DFT into their IC designs. DFT is additional circuitry added to the design to assist in the testing of the IC.
Prior Art FIG. 5 depicts a diagram 500 of an IC similar to that shown in FIG. 1, with an added internal scan capability. Note that a data multiplexer 505 has been added to the input of each register 515. In normal mode (scan enable is de-asserted) the multiplexer 515 connects the input of the register to the output of the combinatorial logic 520. During scan pattern loading (scan enable is asserted), this multiplexer connects the input of the register to the output of an adjoining register. This converts the registers into a single serial shift register which can be loaded through a single scan data input pin 535 and read out through a scan data output pin 540. Note that it is common practice in some designs to break up the scan shift registers into multiple, shorter shift chains with added scan in/out data pins.
Prior Art FIG. 6 depicts a set of data waveforms 600 with an associated clock 615 that may be applied when using the scan pins to test the IC. To execute one scan test pattern, the scan enable signal 605 is asserted (high) to enable the scan input. A test pattern 610 is shifted into the internal registers via the scan data input pin (in the example depicted in FIG. 5, this would require 22 data cycles). After the registers have been loaded, one clock cycle is executed with scan enable de-asserted (low) and with test data 620 applied to the data inputs. This clock cycle captures the outputs of the combinatorial logic that has been stimulated with the data pattern shifted into the registers as well as the data on the data input pin. The data on the output pins 625 is also sampled and compared to expected results on this clock cycle. After the data has been captured, the scan enable signal is asserted again and the captured data 630 is shifted out and tested on the serial data output pin. This process will be repeated several times with different serial scan test patterns.
As previously described, there are two general types of timing parameters to be tested in an IC, the maximum internal data transfer rate and the input/output pin timing. The first, and generally most critical, is the maximum internal data transfer rate. This is the maximum rate in which the IC must be able to propagate signals from the output of one register, through the combinatorial logic, and into the next register stage.
The waveform diagram 700 of Prior Art FIG. 7 shows an example of how this parameter can be tested using scan based patterns. A scan test pattern data is serially loaded into the internal registers with the Scan Enable signal 705 asserted (high) and the clock cycle time set to tscan 710. The clock edge that shifts the last test pattern state prior to the Scan Enable signal 705 being de-asserted (low) is referred to as the launch edge 715, as it loads the internal state which is going to propagate through the internal combinatorial logic to the inputs of the next register stage, which are latched on the next clock edge, the capture edge 720.
The capture edge 720 is brought forward to set the clock cycle for one cycle to tcycle 725. This will test for delay faults that were sensitized by the last pattern state that was loaded prior to the launch clock edge, that is, a pattern state such that the launch causes a signal transition to occur in the path or node being tested on the launch edge 715.
One of the potential problems that can be encountered in the previous technique is the inability to create a pattern state that can cause a transition on a particular path or node. An example of this type of problem is depicted in Prior Art FIG. 8. A combinatorial logic section having an AND gate 805 between the outputs of registers R8 and R9 and the input to register R14. While a transition in the path between R9 to R14 can be tested, the path from R8 to R14 cannot. This is because the output of R8 must be set to a low state prior to the launch edge, and then switched to a high state by the launch edge. However, the previous low state of R8 will be shifted into R9 on the launch edge, preventing the propagation of the transition out of R8 into R14.
To circumvent this problem, a timing pattern 900 as shown in Prior Art FIG. 9, may be used. In this test, the data for the launch pattern is not shifted in from registers, but loaded through the previous stage of combinatorial logic and/or the external data input pins. The launch edge 905 occurs after the scan enable is deasserted, and after the last shift edge 915.
Prior Art FIG. 10 depicts an example of a data input logic section 1000 of an IC, for which input pin timing may be tested. To test the minimum setup time (tsu) of input pin B 1001 before the positive clock transition on Register D 1002, Pin A 1003 and Pin C 1004 must be sensitized one clock cycle prior to the capture cycle. Sensitizing a path infers that the signal path to be tested is adequately enabled, which in the case depicted in FIG. 10 requires that the data input A be set to a low state and data input C must be set to a high state in order to allow a transition on Pin B 1001 to propagate to register D 1002. Typically, only one input pin is tested per scan pattern.
Prior Art FIG. 11 depicts a set of example waveforms 1100 used to test the input pins shown in FIG. 10. Four test segments are shown. In test segment 1101, Input A 1110 is low and Input C 1115 is high one clock cycle before a low-to-high transition is introduced at Data Input B 1120, while scan enable is deasserted. The timing pattern of segment 1101 tests tsu for input B.
In test segment 1102, Input A and Input B are sensitized as in test segment 1101, but the input edge at Input B has been shifted to provide a test for the hold time (thd) on a high-to-low transition 1130.
In test segment 1103, the setup time (tsu) for Input C is tested. In this case, the path is sensitized by having at least one of Input A and Input B set high, so that the transition 1135 at input C will propagate through AND Gate B of FIG. 10.
In test segment 1104, the setup time (tsu) for a high-to-low transition 1150 at Input A is tested. In this case, the path is sensitized by having Input C high 1140, and Input B low 1145.
Prior Art FIG. 12 shows an example of an output pin timing test (tpd and ttoh, FIG. 3) using scan based testing. Typically, only one output pin is tested per scan pattern. To test the maximum propagation delay (tpd) for a specific output pin, the appropriate test pattern required to cause a transition on the output pin under test is shifted into the internal registers. The state of the output pin under test is captured and tested for the expected data state at the specified propagation delay time (tpd) after the clock edge 1205.
The structural test waveforms described can generally be created by existing general purpose ATE systems using their per-pin timing features previously shown in Prior Art FIG. 4. However, requirements for testing a high number of different path delays (tcycle, Prior Art FIGS. 7 and 9), potentially using a different specification for each path, would require more unique time sets than would be practical using a traditional time set memory design.